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收录时间2026-10-24 10:28:09

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文件列表 / 大小

Get Bonus Downloads Here.url 180 B

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/1. Introduction and Overview of VHDL (Description).html 1.65 KB

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/1. Introduction and Overview of VHDL.mp4 151.13 MB 需客户端

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/2. VHDL Data Types and Operators Overview with How to create user defined data type (Description).html 1.37 KB

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/2. VHDL Data Types and Operators Overview with How to create user defined data type.mp4 28.81 MB 需客户端

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/3. Section 1_0 How to Install Xilinx VIVADO and Get 30 day Evaluation License (Description).html 974 B

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/3. Section 1_0 How to Install Xilinx VIVADO and Get 30 day Evaluation License.mp4 44.02 MB 需客户端

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/3. Section 1_0 How to download and install Xilinx VIVADO Design Suit and get 1 month free license_VIVADO.pdf 1.18 MB

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/4. Section_1 Lab Nor Gate in VHDL with VIVADO on ZedBoard (Description).html 1,017 B

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/4. Section_1 Lab Nor Gate in VHDL with VIVADO on ZedBoard.mp4 204.81 MB 需客户端

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/5. Nor Gate Implementation on ZedBoard FPGA (Optional) (Description).html 1,009 B

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/5. Nor Gate Implementation on ZedBoard FPGA (Optional).mp4 33.59 MB 需客户端

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/section 1_ sources_ VHDL Programming with VIVADO and Zynq FPGA/nor_gate.vhd 1.03 KB

~Get Your Files Here !/1 - Section 1_Introduction and Overview of VHDL, VIVADO & Zynq/section 1_ sources_ VHDL Programming with VIVADO and Zynq FPGA/nor_gate.xdc 552 B

~Get Your Files Here !/10 - VHDL Reference Guide (From Basic Design to FSM Examples) from Digitronix Nepal/23. VHDL Reference Guide from Digitronix Nepal (Basic Gate to Sequential Circuits).html 76.44 KB

~Get Your Files Here !/11 - Bonus Lecture/24. What Next (Description).html 660 B

~Get Your Files Here !/11 - Bonus Lecture/24. What Next.html 6.36 KB

~Get Your Files Here !/11 - Bonus Lecture/25. Books and Reference Links (Description).html 741 B

~Get Your Files Here !/11 - Bonus Lecture/25. Books and Reference Links.html 7.95 KB

~Get Your Files Here !/2 - Simulating VHDL code with Testbench/6. Simulation Overview and Lab Simulation of NAND Gate in VIVADO (Description).html 1.13 KB

~Get Your Files Here !/2 - Simulating VHDL code with Testbench/6. Simulation Overview and Lab Simulation of NAND Gate in VIVADO.mp4 180.39 MB 需客户端

~Get Your Files Here !/2 - Simulating VHDL code with Testbench/section 2 sources_VHDL Programming with VIVADO and Zynq FPGA/nand_tb.vhd 1.04 KB

~Get Your Files Here !/2 - Simulating VHDL code with Testbench/section 2 sources_VHDL Programming with VIVADO and Zynq FPGA/nand_vhd.vhd 1.03 KB

~Get Your Files Here !/3 - Conditional Statements in VHDL/7. Lecture Conditional Statement in VHDL (Description).html 1,022 B

~Get Your Files Here !/3 - Conditional Statements in VHDL/7. Lecture Conditional Statement in VHDL.mp4 110.79 MB 需客户端

~Get Your Files Here !/3 - Conditional Statements in VHDL/8. Section 3_2 Lab 31 Decoder Design and Implementation on ZedBoard (Description).html 1,023 B

~Get Your Files Here !/3 - Conditional Statements in VHDL/8. Section 3_2 Lab 31 Decoder Design and Implementation on ZedBoard.mp4 170.22 MB 需客户端

~Get Your Files Here !/3 - Conditional Statements in VHDL/9. Section 3_3 Lab 31 Decoder Demo (Description).html 1.01 KB

~Get Your Files Here !/3 - Conditional Statements in VHDL/9. Section 3_3 Lab 31 Decoder Demo.mp4 29.72 MB 需客户端

~Get Your Files Here !/3 - Conditional Statements in VHDL/section 3 sources_VHDL Programming with VIVADO and Zynq FPGA/Section 3_2_decoder_2 4.vhd 648 B

~Get Your Files Here !/3 - Conditional Statements in VHDL/section 3 sources_VHDL Programming with VIVADO and Zynq FPGA/Section 3_2_decoder_2 4_tb.vhd 962 B

~Get Your Files Here !/3 - Conditional Statements in VHDL/section 3 sources_VHDL Programming with VIVADO and Zynq FPGA/decoder 2_4.png 173.20 KB

~Get Your Files Here !/3 - Conditional Statements in VHDL/section 3 sources_VHDL Programming with VIVADO and Zynq FPGA/simulation of decoder 2 is to 4 in ise vhdl.PNG 24.53 KB

~Get Your Files Here !/4 - Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO/10. Section 4_1 Combinational Circuit Design in VHDL (Description).html 1.16 KB

~Get Your Files Here !/4 - Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO/10. Section 4_1 Combinational Circuit Design in VHDL.mp4 105.81 MB 需客户端

~Get Your Files Here !/4 - Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO/11. Section 4_2 Lab41 Half Adder Design and Implementation with VIVADO and Zynq (Description).html 953 B

~Get Your Files Here !/4 - Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO/12. Half Adder Implementation on ZedBoard Demo.mp4 29.66 MB 需客户端

~Get Your Files Here !/4 - Section 4_A Combinational Circuit Design(Half Adder Design) with VHDL in VIVADO/section 4 sources_VHDL Programming with VIVADO and Zynq FPGA/section 4 Lab 41 half_adder.vhd 247 B

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/13. Seven Segment Decoder Design in VHDL (Description).html 729 B

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/13. Seven Segment Decoder Design in VHDL.html 24.43 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/13. Seven Segment Display with Nexys 2.pdf 477.80 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/13. Seven Segment Display_4_digit with Nexys 2_V2.pdf 361.17 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/Sources/clkdiv.vhd 1.69 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/Sources/fsm.vhd 1.84 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/Sources/mux44.vhd 2.05 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/Sources/seven_seg_driver.vhd 2.45 KB

~Get Your Files Here !/5 - Section 4_B Seven Segment Decoder Design and Display Interfacing on VHDL/Sources/seven_segment.vhd 1.57 KB

~Get Your Files Here !/6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)/14. Section 5 Structural Design with VHDL with Lab on Designing Full Adder using Hal (Description).html 1.12 KB

~Get Your Files Here !/6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)/15. Section 5 Lab 51 Structural Design Lab for Full Adder Demo (Description).html 1.55 KB

~Get Your Files Here !/6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)/15. Section 5 Lab 51 Structural Design Lab for Full Adder Demo.mp4 41.42 MB 需客户端

~Get Your Files Here !/6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)/section 5 sources_VHDL Programming with VIVADO and Zynq FPGA/Full_Adder.vhd 573 B

~Get Your Files Here !/6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)/section 5 sources_VHDL Programming with VIVADO and Zynq FPGA/full_adder_tb.vhd 2.67 KB

~Get Your Files Here !/6 - Section 5 Structural Design with VHDL (Full Adder Design using Half Adder)/section 5 sources_VHDL Programming with VIVADO and Zynq FPGA/half_adder.vhd 278 B

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/16. Section 6_1 Sequential Circuit Design in VHDL (Description).html 1.05 KB

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/16. Section 6_1 Sequential Circuit Design in VHDL.mp4 115.67 MB 需客户端

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/17. Section 6_2 Lab 61 BCD Counter Design and Implementation (Description).html 1.38 KB

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/17. Section 6_2 Lab 61 BCD Counter Design and Implementation.mp4 146.92 MB 需客户端

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/18. BCD Counter Implementation on ZedBoard Demo.mp4 21.15 MB 需客户端

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/section 6 sources_VHDL Programming with VIVADO and Zynq FPGA/bcd_vhd.vhd 1.41 KB

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/section 6 sources_VHDL Programming with VIVADO and Zynq FPGA/bcd_xdc.xdc 767 B

~Get Your Files Here !/7 - Section 6 Sequential Circuit Design (BCD Counter Design & Implement) with VHDL/section 6 sources_VHDL Programming with VIVADO and Zynq FPGA/section 6_1 3 bit shift register.vhd 853 B

~Get Your Files Here !/8 - Section 7 Finite State Machine Design Sequence Detector Design Implement in VHDL/19. Section 7 FSM Design in VHDL Lab 71 Sequence Detector Design (Description).html 1.46 KB

~Get Your Files Here !/8 - Section 7 Finite State Machine Design Sequence Detector Design Implement in VHDL/19. Section 7 FSM Design in VHDL Lab 71 Sequence Detector Design.mp4 143.82 MB 需客户端

~Get Your Files Here !/8 - Section 7 Finite State Machine Design Sequence Detector Design Implement in VHDL/19. VHDL_Reference_Guide_v3_Aug 2017 Prepared_by_Digitronix_Nepal.pdf 1.87 MB

~Get Your Files Here !/8 - Section 7 Finite State Machine Design Sequence Detector Design Implement in VHDL/Section 7 State machine design sequence detector_VHDL Programming with VIVADO and Zynq FPGA/seq_det.xdc 887 B

~Get Your Files Here !/9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)/20. ALU Design (ALU Overview and 8 Bit ALU Design)-I (Description).html 845 B

~Get Your Files Here !/9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)/20. ALU Design (ALU Overview and 8 Bit ALU Design)-I.mp4 101.81 MB 需客户端

~Get Your Files Here !/9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)/21. ALU Design (ALU Overview and 8 Bit ALU Design)-II (Description).html 869 B

~Get Your Files Here !/9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)/21. ALU Design (ALU Overview and 8 Bit ALU Design)-II.mp4 27.34 MB 需客户端

~Get Your Files Here !/9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)/22. ALU Design Lab 81 N bit ALU Design (Description).html 745 B

~Get Your Files Here !/9 - ALU Design (8 bit & N bit ALU Design with Wallace Tree Multiplication Algorithm)/22. ALU Design Lab 81 N bit ALU Design.mp4 236.53 MB 需客户端

~Get Your Files Here !/Bonus Resources.txt 70 B